1. Field of the Invention
The present invention relates to a semiconductor device embedding a dynamic random access memory (DRAM), in particular, a system circuit for improving data retaining characteristics of the DRAM.
2. Description of the Related Art
In general, data retaining characteristics of DRAMs has been decided, for example, by the poorest one of the memory cells to be mounted.
The characteristics of DRAMs have been decided by a leakage current characteristic caused by a crystal defect in the memory cell and observed as a random defect of a single bit at a memory cell matrix.
Moreover, a defective cell caused by these factors cannot be prevented even if an improvement of the producing processing is performed.
Therefore, in a general DRAM, the yield has been secured by replacing a cell having a poor data retaining characteristic with a redundancy cell.
However, the method has to add the redundancy cell in accordance with the number of defect to be secured, and the increase of area due to that becomes a disadvantage.
Further, since the number of the redundancy cells to be mountable is restricted, a substantial improvement of the retention cycle is difficult.
Due to this, in recent year, it has been restricted to a step in which the power consumption of a mobile application use DRAM in a standby mode is decreased by extending the refresh cycle drastically in the standby mode.
In recent years, as a data-retention controlling circuit for DRAM, a semiconductor integrated circuit device having an ECC circuit and a refresh period setting circuit had been proposed (refer to, for example, Japanese Patent Unexamined Publication (Kokai) No. 2002-56671).
The ECC circuit of the semiconductor integrated circuit device is performed with the following first and second operations: the first operation is that the ECC circuit is started when entering in a data retention mode of the memory circuit, a plurality of data retained in the memory circuit are read, and check bits for an error detecting and correcting are generated and recorded; and a second operation is that the circuit is started when returning from the data retention mode to a normal operation wherein a read or write operation is performed between the other circuits, reading a plurality of data and the check bit retained in the memory circuit is read, an error bit of data is corrected, and writing the data is written into a corresponding memory cell.
The refresh-period setting circuit sets a period used with the check bit in the ECC circuit and extended within the tolerance of an error generation, and it is made to perform a refresh operation.
The semiconductor integrated circuit system disclosed in Japanese Patent Unexamined Publication (Kokai) No. 2002-56671 can improve the data retaining characteristics of a DRAM and decrease power consumption, but it must be a prepared exclusive pattern generating circuit. When designing a circuit able to generate efficient patterns, the circuit size becomes large, and when making the circuit size small, a pattern becomes redundant and an operating time increases, so that it is caught in a dilemma. Then, as usual, only the minimum necessary circuits are mounted, but the pattern becomes redundant as mentioned above, and the operation time becomes a disadvantage.
Due to the above mentioned factors, the semiconductor integrated circuit system in the above document has the following disadvantages: (1) to mount the exclusive circuit causes an increase in excessive circuits; and (2) keeping the circuit size small, causes an increase in operating time.